ntain bits that are carried bases on the result of an instruction. They also contain information on interrupts to information to get a priority on less important information.All these steps are added to the program counter. Between each stage of this cycle the data is carried on busses that take it to the address part or the data part of the cycle. There are different types of bus here are two examples.The Address Bus carries addresses so that the required locations can be accessed so they can read or write data. The Data Bus transfers the information to the correct memory location.This then means from the diagram the fetch part of the cycle carries all the data to the correct one of the execute part of the cycle. The fetch part of the cycle is common while the execute part of the cycle varies. The fetch-execute cycle is as follows:The address of the instruction is copied from the PC and held in the MAR. The instruction (e.g., add x), is placed into the MDR where it is temporarily stored.The instruction (add x), is then copied to the CIR.The PC now moves on to the next instruction, (e.g., add y).While in the CIR the instruction is decoded, this determines what the instruction has to do, (add).The operand part of the instruction, (x) is then copied to the MAR.The data item (e.g., 3), whose address is still stored in the MAR, is copied to the MDR.The item held in the MDR (3) is then added to the accumulator.The process is then repeated for the next instruction, (add y).The accumulator works as follows:For example, value x = 3, y = 4, z = 7 Instructions - add x, add y, add zAccumulator Value = 0 = 3 = 7 = 14The root of the single cycle processors problems:The cycle time has to be long enough for the slowest instruction (load)Solution:Break the instruction into smaller stepsExecute each step (instead of the entire instruction) in one cycleCycle time: time it...
