0SET (stores 1)0 0 1RESET (stores a 0)(c) Transition table CP(CLK) D (Input) Q (Output) (d) WaveformProcess for Standard, TTL and CMOSD(elay) Flip-Flop (Standard)The circuit of a D Type flip-flop has already been given to us. We are required to construct the given circuit using Design Architect ( DA). The constructed circuit is shown in figure 1 printed out using the lab printer.Next, a symbol of the circuit is created using DA from the menu Miscellaneous followed by Generate Symbol. The created symbol is than modified. The modified symbol is shown in figure 2.Next, Quicksim is activated mainly to invoke forces on the constructed circuit and to Trace as well as to analyze the output of the circuit through waveforms.The saved file of the constructed circuit using DA is opened in Quicksim. Firstly, the function TRACE is used to trace PRE, CLR, CLK, D, Q, QB. After this a Trace box will appear at bottom lower left of the screen. This is where the simulated waveforms will apprear.Forces is then added to each of the traced components except for Q and QB.ComponentValue of ForcePRE1 at time 0CLR0 at time 0 and 1 at time 35CLKPeriod 100, 50% duty cycleDPeriod 160, 50% duty cycleAfter forcing the components with the required values, type RUN 800. The waveforms will appear exactly the same as the required waveforms printed out in figure 3. (please note that the traced components are included in the waveform results)As we can see clearly in figure 3, the inputs of D are copied straight to the output Q. Transitions occurs at every positive-edge of the clock. Therefore the waveforms agree with the specification mentioned above.Next, an experiment is done by changing the PRE and CLR to low. Theoretically, an illegal output would happen. The traced output with the above configuration is printed in figure 4. We can see that when both PRE and CLR are low resulting ...
