the output of Q and QB to be high. QB is defined to be the opposite of Q. However this happens ( both are High) due to the fact that both PRE and CLR are set to low. Therefore it is said that the output gives an illegal operation. This is because PRE and CLK cannot be set to low at the same time. PRE has to be HIGH to give an output.The next operation done to the D flip-flop is to analyze the output when the CLK and input D changes simultaneously. We do this by adding force to the CLK and D by using the Stimulus in the menu and then clicking on ADD CLOCK(remember to delete the previous forces). We set the period of CLK to be 100 with 50% duty cycle and 150 is set for D. The output waveform is printed in figure 5. By looking at the Q output waveform, we note that at every positive rising edge of CLK and D which in this case happens simultaneously gives an oscillated output. Why does this happen? We have to first understand the basic concept of Timing factors. Below is a graphical explanation of the time behavior of cell. CLK Input State Time Behavior of CellSetup time (tsu) is the minimum interval from the stabilization of the cell input to the triggering edge of the clock.Hold time (th) is the minimum time interval from the triggering edge of the clock to a subsequent change in the input to the cell.Propagation delay (tw) is the time interval from the triggering edge of the clock to the stabilization of the new state(cell output). When it is appropriate, we distinguish low-to-high and high-to-low propagation delays. After reading through the time behavior of cell (taken from Introduction to Digital Systems by Milos Ercegovac, Tomas Lang and Jaime H.Moreno) we now can conclude that the oscillation happens due to the fact that the output cannot be determined whether to set to high or low...
