th Q and QB are HIGH. This is because that PRE has to be set to HIGH for an output.Another similarity between standard and CMOS D Flip-Flop is that when CLK and D occurs simultaneously, the output at that point oscillates. This is explained in the above timing behavioral diagram. As for the TTL, output is invalid.The most significant difference is the delay time. The delay for TTL is much shorter as compared to CMOS.Time management is very essential in completing this assignment. This is because only a specific of time is allocated for each student to use the licensed Mentor Graphics. Furthermore, it gives students an in depth understanding of the operation, characteristics of the D Flip-Flop, TTL and CMOS and configurations.It is essential to take this given opportunity to master the software as to assist us in completing 2nd assignment....
