respectively. The output is still valid.As we can see in figure 11, the output is invalid because Q is not completely the complement of QB This happens when the CLK period is set to 34ns.Another explanation is through basic calculation. We know that the rise time and fall time delay for the NAND gates are 17 and 15 respectively. With the help of the diagrams below, we would have a better understanding.CLKQ Minimum Operating PeriodFor the data to be copied to the output, the time taken for D to reach HIGH is 17ns and to reach LOW is 15ns. Adding both the time we get 33ns. Which means that the minimum period would be 34ns. Any period lower then that, output would be invalid.CMOSThe circuit in TTL configuration is used. The previous forces of the NAND gates and buffer are replaced by values as shown below. The circuit is shown in figure 12.GateRiseFallNAND160160BUF8040The procedures are repeated as in simulating the standard D flip-flop in the beginning.However, due to the fact that the Trace is initially in nanoseconds and therefore output waveform cannot be seen clearly, the environment is changed to microseconds.The output waveform is shown in figure 13.The CLK period is set to 100us.When PRE and CLK are set to LOW, invalid output occurs. Result shown in figure 14When the CLK and D of CMOS changes simultaneously, oscillation happens. Figure shown in figure 15.The maximum operating frequency is found to be 1/0.33us = 3.03Mhz shown in figure 16Comments and ConclusionBy completing the above assignment, it has given the user an in-depth understanding on the operation on standard TTL and CMOS. Both devices are basically constructed from the standard D-flip flop configuration.By experimenting with the 3 different configured device, we can conclude that they have significant similarities and differences. One of which is that similar results occur when PRE and CLK are set to LOW. The output Q is not the exact complement of QB. Bo...
