. It is set in such a way that whenever CLK and D triggers to High simultaneously, oscillation occurs (figure 5). The lack of setup up time is the reason why oscillation happens.TTLThe next section of the assignment takes a look at TTL delays. The standard D flip-flop file which was saved in the beginning is copied into a new file called dfilp_ttl. This is done by opening the previous dflip file and saving it, typing the path name as dflip_ttl.Delays are inserted by clicking on change value in Design Architect. Select all the numbers beside the gates (initially 0) and then change the values. The upper number is the Rise time and the lower number is the Fall time. By default the values are in nanoseconds.The values for the 2 gates are tabulated below.GateRiseFallNAND1715BUF206In order for the delays to take effect on the circuit, we have to first activate the delays by clicking on SETUP, Analysis and then click on Delay. Trace all the components and type RUN 800. The output waveform is shown in figure 6.It is seen here that with delay the output Q is shifted to the right. However, as marked on the waveform (A) as the CLK is triggered as D goes low, the output Q should go low. Due to the insufficient setup time for D, the output Q have no choice but to go high.When the CLK and D occurs simultaneously, invalid operation occurs at the output. Q is not the exact complement of QB, shown in figure 7. Similar results are acquired as PRE and CLK goes low, shown in figure 8.The minimum period for the circuit to work properly is found to be 34.1ns. Basically, whatever is lower than the minimum period which is also the maximum operating frequency(1/34ns = 29.41Mhz) , the circuit will not work correctly. The output would be invalid. How do we find the maximum operating frequency? 1 way is to go through Trial and Error. By reducing the period until we get an invalid output. As shown in figure 9 and figure 10 the period of CLK is reduced to 50 and 40 ...
